Through-Silicon Vias

Vertical interconnects that enable 3D chip stacking

A through-silicon via is a vertical electrical connection that passes completely through a silicon wafer or die. TSVs enable 3D integration—stacking multiple chips and connecting them with short, dense interconnects instead of routing signals around the edges.

Why Go Vertical

Traditional chip packaging connects dies side-by-side using wire bonds or flip-chip bumps around the periphery. Signal path lengths are measured in millimeters. Pin counts are limited by the die perimeter.

TSVs change the geometry. Connections run straight up and down through the silicon. Path lengths shrink to tens of micrometers. Pin density scales with area, not perimeter.

The Manufacturing Process

Creating a TSV requires drilling a hole through silicon, insulating it, and filling it with metal.

  1. Etching: Deep reactive ion etching (DRIE) bores a high-aspect-ratio hole—typically 5-10 micrometers wide and 50-100 micrometers deep.

  2. Insulation: A thin oxide layer prevents shorts between the via and the silicon substrate.

  3. Barrier and seed: Metallic layers prepare the surface for copper deposition.

  4. Filling: Electroplating fills the via with copper from bottom to top.

  5. Planarization: Chemical-mechanical polishing creates a flat surface for bonding.

Applications

HBM is the highest-volume TSV application today. Each memory stack contains thousands of TSVs connecting DRAM dies to the logic base.

Advanced packaging like Intel's Foveros and TSMC's SoIC use TSVs to stack logic on logic—putting different process nodes in a single package.

The Challenges

Thermal expansion mismatches stress the vias. Keep-out zones around TSVs reduce usable silicon area. Testing partially completed stacks is difficult. Yield compounds multiplicatively with each stacked die.

Despite these challenges, TSVs have become essential for high-performance computing. When bandwidth density matters more than cost per transistor, going vertical wins.